- Substrate interconnections have 2µm half pitch or less
- No packages or heat sinks
- Impervious to water
- Lowest thermal resistance in the industry
The substrate is patterned with redistribution layers (RDLs) having a half-pitch of 2µm or less, to accommodate flip chip mounted components such as high bandwidth memories (HBMs) having a bump pitch of 40µm or less. The circuit assemblies comprise semiconductor devices of all types, including bare die, chiplets, and stacked devices including interposers, multi-level stacks and bridge devices. The drawing scale is expanded in the x-direction to reveal thin layers such as RDLs, backside power distribution layers, and the outer metallization layer.
Following flip chip assembly and rework, a filler material such as epoxy molding compound (EMC) is applied between the components in a molding process; it provides mechanical support for subsequent back-grinding and polishing operations. Following these operations, the circuit assemblies have a height of approximately 1mm. The polished planar surfaces extend across the faces of the circuit assemblies, measuring approximately 3.4 x 18 inches in the proposed server design.
Thin film layers are optionally fabricated on the polished surfaces to provide backside power distribution. Through silicon vias (TSVs) and conducting pillars, vias, or pins provide continuity between front and back side conductors.
The metallization layer may be copper that is applied by placing semi-complete modules in a carousel jig that is rotated inside a deposition chamber; this layer may be plated up to provide a stable and non-porous protective layer that is impervious to water.